The disclosed embodiments of the present invention relate to recording data into and/or reading data from a storage device, and more particularly, to a storage controller having an encoding circuit/decoding circuit programmable to support multiple finite fields, multiple codeword lengths and/or multiple error correction capabilities and related method thereof.
Error detection and correction techniques are employed to effectively correct errors caused by various factors to obtain error-free data. Taking a flash memory for example, continuous improvements in price/performance for the flash memory have enabled the flash memory to become the long term storage of choice for many applications. However, during the fabrication, the flash memory may contain defects (e.g., defective memory cells), and more defects may appear during the device lifetime, thereby limiting its usage. To manage these defects and to achieve efficient and reliable operation, the memory system typically uses error detection and correction techniques to ensure reliable data reproduction.
In a typical flash memory device, Bose-Chaudhuri-Hocquenghem (BCH) coding is commonly employed to detect and correct data errors. The codeword length and the error correction capability of the BCH coding are determined by the following formula: n−k≦m·t, where n represents a BCH codeword length (e.g., a total length of user data and parity), k represents a length of user data, m represents a finite field (also called a Galois field), and t represents an error correction capability.
With regard to the single-level-cell (SLC) flash memory devices, the ECC requirements of SLC flash devices fabricated by different manufacturers are similar. As the required ECC requirements are similar, the same control chip which provides a BCH code in the finite field GF(2^3) can be employed to meet the ECC requirements of SLC flash devices fabricated by different manufacturers.
However, regarding the multi-level-cell (MLC) flash memory devices, MLC flash devices fabricated by different manufacturers have different page lengths and ECC requirements. In addition, different ECC codeword lengths will require different finite fields. For example, a user data length of 512 bytes generally requires the use of a finite field GF(2^13), a user data length of 1K bytes generally requires the use of a finite field GF(2^14); and a user data length of 2K bytes generally requires the use of a finite field GF(2^15). Therefore, a conventional control chip of an MLC flash memory device only supports a single finite field and a single error correction capability required by the MLC flash memory device. That is, the same control chip which supports a single finite field and a single error correction capability cannot be applied to different MLC flash devices with different page lengths and ECC requirements.
The conventional control chip supporting a single finite field and a single error correction capability lacks flexibility. For example, a control chip employing a single and fixed finite field fails to support a longer codeword length, and uses more parity bits when supporting a shorter codeword length, which wastes the spare area of the flash memory device. Moreover, a control chip employing a single and fixed error correction capability is unable to dynamically adjust the error correction capability in response to requirements of different applications.
Therefore, there is a need for a programmable storage controller which can satisfy different ECC requirements to achieve the optimum data protection.